Verification IP (IMS-09) - PR903426-2380-P
- CPV
- 48321000 — Computer-aided design (CAD) software package
- Region
- Duisburg, Kreisfreie Stadt
- Procedure
- open
- Published
- Apr 17, 2025
- Deadline
- 19 May 2025, 08:00
Description
Tooling and IP Blocks for verification of safety and security features of digital designs, RISC-V microcontrollers and extensions and platform features of System on Chips. To check and guarantee fail safe operation as well as fault detection and correction, classical HDL verification IP as well as formal verification will be used. The support for the RISC-V architecture must be ensured. At the end of the project, the IP provider is requested to make the tooling and rule set definitions available...
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About this buyer
Fraunhofer-Institut für Angewandte und Integrierte Sicherheit AISEC published 61 tenders in the last 12 months.
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